Low Cost ASIC Development

We offer a highly competitive low cost path from initial idea to final silicon. This is achieved by adopting open source tools throughout our design flow, and taping out on a more mature, and hence economical, process node - 130nm.

The design flow is detailed below where it can be seen to comprise entirely of open source tools, hence elliminating high development tool costs from commercial EDA vendors. Then, by taking advantage of the fact that most analog centric ASICs don't need to run on the most advanced process nodes, we elliminate the exponentially increasing mask set costs associated with such nodes, by taping out on the more mature 130nm. Combined, these two factors enable us to offer our customers the most economical path from initial idea to final silicon, delivered as bare die or QFN packages in quantities of 100 (prototype), 10k (low volumne),  100k (medium volume) or >1M (high volume).

An example costing for 100 parts + 5 eval boards = $10k + design development costs, the latter of course being dependant on the ASICs complexity.

So if you are looking to prototype an idea, reduce your PCBs BOM or maximise your products gross margins, please do not hesitate to contact us.