Mixed Signal IC Design Contracting & Consulting

Reduce development time by hiring a mixed signal IC design contractor / consultant with 20 years experience, spanning multiple nodes (180 down to 7nm) across multiple founderies. 

 

Specific expertise includes (but is not limited to) the following:

 - Amplifiers: Single ended and fully   differential OTAs / opamps with class A / AB output stages / Miller & Ahuja compensated

- Voltage references: Standard / sub-1V Bandgap architectures with high PSR (40dB)

- Current references: PTAT / CTAT & V2I's with high PSR (40dB)

- LDOs: Input / output pole dominant, standard / capless architectures with low noise (15uVrms) & high PSR (40dB)

- Buck converters: PWM control (10MHz)

- Current sensing: High side / low side / CT / DT architectures with high CMR (110dB) & low noise (15nV/rtHz)

- Sigma delta ADCs: CT (4th-order) / DT (2nd order)

- DACs: Resistor based (ladders / R2Rs & ternary RDACs) / high speed current steered

- PLLs: fully differential, 3rd order analog CP-PLLs

- HV design: Up to 70V (CSA's, level shifters, HV references)

- Temperature sensors: BJT & MOS based, accurate to 1degC / single point / distributed

- Comparators: Continuous & dynamic (strong arm / Schinkel / Elzakker) architectures

- Integrators: Continuous & switched cap (parasitic insensitive, autozeroed) architectures

- Charge pumps: 4-stage Peliconi based

- Clock distribution: 14GHz with low jitter (50fs), skew & duty cycle correction (2ps)

- ABUS networks: Low leakage (channel & GIDL), high accuracy (1%), servicing FPGAs

- Process monitoring: Ring oscillator based characterising RC spreads

- Offset compensation: Chopping / autozeroing / DEM / CDS & triming (< 50uV)

- Housekeeping blocks: POR, clock detection, level shifters & oscillators

- Layout: WPE / LOD / LU / EM / floorplanning / guidance / validation

- Reliability: TDDB / BTI / HCI / SHE & HTOL char / failure analysis

- Lab char: ADCs (ramp testing) and temperature sensors